1. Field of the Invention
The present invention relates to a semiconductor device used as an element for a memory or as an element for a digital logic circuit.
In this specification, a quantum box is defined as a structure which confines electrons or holes in a size of not more than 1000 .ANG. in three directions normal to one another.
2. Description of the Background Art
FIG. 19 is a schematic sectional view showing structure of a floating gate MOS transistor used as a memory cell of an EEPROM (Electrically Erasable and Programmable Read Only Memory).
In FIG. 19, a source region 72 and a drain region 73 formed of n.sup.+ layers are formed at a certain interval in the surface of a p-type Si substrate 71. A floating gate 75 is formed on the region between the source region 72 and the drain region 73 through a tunnel oxide film 74, and further a control gate 77 is formed through a thick oxide film 76. The reference numeral 78 indicates an insulating film for element isolation.
FIGS. 20(a), (b), and (c) show energy band diagrams in writing, holding and erasing of the floating gate MOS transistor of FIG. 19, respectively. In FIG. 20, E.sub.F indicates the energy level of the Fermi level, E.sub.C indicates the energy level at the lower end of a conduction band and E.sub.V indicates the energy level at the upper end of a valence band.
The source region 72 is supplied with a source potential (ground potential) V.sub.S and the drain region 73 is supplied with a drain voltage V.sub.D. Thus, a channel is formed between the source region 72 and the drain region 73.
When writing, a high positive gate voltage V.sub.CG is applied to the control gate 77. Thus, electrons are injected by the tunneling phenomenon into the floating gate 75 from the channel formed between the source region 72 and the drain region 73. In a holding state, electrons are accumulated in the floating gate 75. When erasing, a negative high gate voltage V.sub.CG is applied to the control gate 77. Thus, electrons in the floating gate 75 are emitted into the channel formed between the source region 72 and the drain region 73.
In this way, the floating gate MOS transistor operates as a writable and erasable non-volatile memory element.
On the other hand, the SET (Single Electron Tunneling) phenomenon has attracted special interest recently. The SET phenomenon will now be briefly described. If capacitance of a fine junction is taken as C, then the Coulomb energy U(n) of the fine junction having n electrons is given by the equation below. EQU U(n)=(ne).sup.2 /2C (1)
Now, e is a unit electric charge amount. From the equation (1), the Coulomb energy .DELTA.U necessary to add an electron to this fine junction is given by the equation below. EQU .DELTA.U=U(n+1)-U(n)-e.sup.2 /2C (2)
Generally, as the capacitance of the tunnel junction is relatively large, the Coulomb energy .DELTA.U of the equation (2) is smaller than the thermal energy. Accordingly, the electron is thermally excited and can tunnel the fine junction. Hence, even if an electron is added to the fine junction with the Coulomb energy .DELTA.U, the electron will be emitted from the fine junction by the tunneling.
Recently, however, the progress in the fine processing technique has enabled formation of a fine junction of about 1000 .ANG.. For example, in the case of a fine junction having its one side of 1000 .ANG. and a barrier thickness 100 .ANG., the Coulomb energy .DELTA.U corresponds to thermal energy of about 10 K. Accordingly, if the temperature is decreased to 10 K or below, the electron can not freely tunnel the fine junction any more. In this case, electrons are accumulated in the fine junction one by one by tunnelling every time the Coulomb energy .DELTA.U is externally supplied. These days, various elements such as a single electron transistor etc. utilizing the SET phenomenon are suggested and manufactured by way of trial.
In the above-described floating gate MOS transistor, it is necessary to have the tunnel oxide film 74 thick in order to prevent electrons from escaping by tunneling from the floating gate 75 into the channel in the holding state. Therefore, it is necessary to apply a high gate voltage V.sub.CG to allow electrons to tunnel in writing and erasing.
This will result in increased power consumption and low operation speed. Furthermore, a high electric field produced when the high voltage is applied deteriorates the tunnel oxide film 74 and the number of times of writing and erasing will decrease. As shown in FIG. 21, the number of times of writing and erasing of the floating gate MOS transistor is about 10.sup.5 times.
Further, as the operation of the above-described floating gate MOS transistor requires a large number of electrons, the element will not operate when the element is miniaturized to a certain extent for higher integration. Although various elements are suggested and manufactured by way of trial which use the SET phenomenon for higher integration, practical elements have not actually been developed yet because of various problems, such as those in the manufacturing technique, operation temperature, etc.